This invention relates to apparatus for encoding sequences of unconstrained data into sequences of encoded data obeying RLL (1,7) encoding rules.
As is known, conventional computer systems utilize magnetic disks for data storage. In order to maximize the amount of data stored on a disk, many such systems normally employ some form of run-length-limited (RLL) coding to encode data prior to entry onto a disk, which provides particularly dense packing of disk-stored data.
In the family of RLL codes, the (1,7) format is gaining increasing acceptance in the industry as the preferred RLL coding format for present magnetic disk technology. In employing the RLL (1,7) coding format, a sequence of unencoded binary data is converted into an encoded bit string in which each one in a coded bit sequence must be separated from the nearest adjacent one by at least one, but no more than seven zeros. In this format, the most efficient coding rate results when every two unencoded data bits are converted into three coded bits. Conversely, in the decoding process, three coded data bits are converted into two decoded data bits. This technique is taught in detail in U.S. Pat. No. 4,413,251 to R. L. Adler et al, which is assigned to the assignee of this patent application.
A typical prior art architecture employing RLL (1,7) coding in a magnetic disk storage system is illustrated in FIG. 1. As is typical, unencoded data from a data processing system is provided to the encoder section of an encoder/decoder (ENC/DEC) through a serializer/deserializer (S/D). When provided to the serializer/deserializer, the data is normally in parallel byte form, which must be serialized into a sequence of 2-bit groups. Each 2-bit group provided to the encoder results in the provision of three encoded bits that go to a buffer (B) for serialization into an encoded, bit-wide data string that is processed by drive circuitry for writing onto a magnetic disk. In the industry, this is referred to as bit-by-bit encoding. When data is read from the disk, a bit-wide encoded data string is provided through the buffer B in the form of successive groups of three encoded bits to the decoder section of the encoder/decoder. Each successive group of three encoded bits is decoded to a group of two data bits (bit-by-bit decoding). The succession of bit pairs from the decoder are converted by the serializer/deserializer into a succession of bytes that are forwarded to the data processing system.
An artifact of the bit-by-bit coding system of FIG. 1 is the requirement for at least two conversion clocks: an f.sub.C clock for the encoded bit channel and a 2/3 f.sub.C clock for the transfer of data between the serializer/deserializer S/D and the buffer B.
The f.sub.C clock can be derived conventionally from a disk servo clock while writing information to a disk or from encoded read data obtained from a disk while reading information from the disk. Normally, f.sub.C is obtained under either circumstance through a voltage-frequency oscillator (VFO).
The 2/3 f.sub.C clock is usually derived by use of a second VFO synchronized to the f.sub.C clock. This imposes an added hardware requirement and requires the settling times of two VFO's to be accounted for when the timing source to the f.sub.C VFO is switched.
Moreover, the FIG. 1 architecture requires an extra format conversion for unencoded and decoded data passing between the serializer/deserializer and encoder/decoder, further adding complexity to the system.
Further, the typical prior art RLL (1,7) encoder consists of a finite-state machine whose internal state is described by three state bits. Plural state bits increase the logic and storage hardware requirements of the encoder, which make it awkward for being cascaded in parallel to provide byte-wide encoding.